10:00 - 10:05 Welcome message
10:05 - 11:00 Keynote 1: Nikil DUTT, Self-Awareness for Heterogeneous MPSoCs: A Case Study using Adaptive, Reflective Middleware
11:00 - 11:15 Coffee break
Session 2
11:15 - 12:00 Keynote 2: Tim KOGEL, Building Smart SoCs - Using Virtual Prototyping for the Design of SoCs with Artificial Intelligence Accelerators
12:00 - 12:20 Rabab Bouziane, Erven Rohou and Abdoulaye Gamatie, Compile-Time Silent Store Elimination for Energy Efficiency: an Analytic Evaluation for Non-Volatile Cache Memory
12:20 - 12:45 Gereon Onnebrink, Rainer Leupers and Gerd Ascheid, ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models
12:45 - 14:00 Lunch
Session 3
14:00 - 14:45 Keynote 3: Alberto Bosio, Cross-Layer system-level reliability Estimation
14:45 - 15:00 Giovanni Liboni, Julien Deantoni, Antonio Portaluri, Davide Quaglia and Robert De Simone, Beyond Time-Triggered Co-simulation of Cyber-Physical Systems for Performance and Accuracy Improvements
15:00 - 15:15 Ahmet Erdem, Davide Gadioli, Gianluca Palermo and Cristina Silvano, Design Space Pruning and Computational Workload Splitting for Autotuning OpenCL Applications
15:15 - 15:30 Vittoriano Muttillo, Giacomo Valente, Daniele Ciambrone, Vincenzo Stoico and Luigi Pomante, HEPSYCODE-RT: a Real-Time Extension for an ESL HW/SW Co-Design Methodology
15:30 - 16:00 Coffee break
Session 4
16:00 - 16:45 Keynote 4: Guy Bois, Space Codesign Systems and Polytechnique Montréal
16:45 - 17:00 Irune Yarza, Mikel Azkarate-Askasua, Kim Grüttner and Wolfgang Nebel, Real-Time Capable Retargeting of Xilinx MicroBlaze Binaries using QEMU
17:00 - 17:15 Asif Ali Khan, Fazal Hameed and Jeronimo Castrillon, NVMain Extension for Multi-Level Cache Systems
17:15 - 17:30 Work in progress: Alexandre Chabot, Ihsen Alouani, Smail Niar and Reda Nouacer, A Fault Injection Platform for Early-Stage Reliability Assessment
