ZeBu Hybrid Emulation: Shift-left your Architecture Exploration, Software Development and System Validation with Synopsys Hybrid Solutions - Alejandro Nocua, Synopsys.
Session 2: Papers Session : 10:50-12:30
10:50: Non-intrusive runtime monitoring for manycore prototypes,
Fabian Lesniak, Juergen Becker, Nidhi Anantharajaiah and Tanja Harbaum
11:15: Faster Functional Simulation With Cache Merging,
Gustaf Borgström, Christian Rohner and David Black-Schaffer
11:40: Fast Instruction Cache Simulation is Trickier than You Think,
Marie Badaroux, Julie Dumas and Frederic Petrot
12:05: Automatic DRAM Subsystem Configuration with irace,
Lukas Steiner, Gustavo Delazeri, Iron Prando Da Silva, Matthias Jung and Norbert Wehn
Session 3: Keynote Session : 14:00-14:45 am
Challenges in modeling HPC SoCs: An experience report on using Gem5 - Manolis Marazakis and Polydoros Petrakis, FORTH
Session 4: Papers Session : 14:50-16:30
14:50: Entropy-Based Analysis of Benchmarks for Instruction Set Simulators,
Nils Bosbach, Lukas Jünger, Rebecca Pelke, Niko Zurstraßen and Rainer Leupers
15:15: Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration,
Johannes Knödtel and Marc Reichenbach
15:40: An Analytical Model of Configurable Systolic Arrays to find the best-fitting Accelerator for a given DNN Workload,
Tim Hotfilter, Patrick Schmidt, Julian Höfer, Fabian Kreß, Tanja Harbaum and Juergen Becker
16:05: Fast-Yet-Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms,
Quentin Dariol, Le Nours Sébastien, Domenik Helms, Ralf Stemmer, Sebastien Pillement and Kim Gruettner11:30 - 12:30 Session 2
