Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Title: (Re-)Configurable Processor Arrays On-Chip - Co-Design of Architectures and Compilers
11:00 - 11:30 Coffee break
11:30 - 12:15 Keynote 2:
Marc Casas Guix, Barcelona Supercomputing Center (BSC), Spain
Title: Analysis and Simulation of Architectures Supporting the RISC-V “V” Vector Extension.
12:15 - 12:55 Paper Session 1
(12:15 - 12:35) Towards Accurate Static Power Model on Multi-Core Operating Systems, G. Barret, D.Chillet, R. Picard and J. Penhoat
(12:35 - 12:55) DRAMPower 5: An Open-Source Power Simulator for Current Generation DRAM Standards, L. Steiner, T. Psota, M. Mörz, D. Christ, M. Jung and N. Wehn
13:00 - 14:00 Buffet Lunch
14:00 - 14:45 Keynote 3:
Cristina Silvano, Full Professor of Computer Science and Engineering at Politecnico di Milano
Title: Accelerators for Deep Learning on the Edge
14:45 - 15:25 Paper Session 2
(14:45 - 15:05) Aspycot: A Spike and Python Co-simulation Testbench for Hardware Monitoring IPs, T. Biton, S. Pillement, O. Gilles, N. Kosmatov and D. Gracia Pérez
(15:05 - 15:25) Execute Your Darlings: Dynamic Execution of High-Level Formal Specifications for Validation and Early Prototyping, R. Kunzelmann, Z. Tahoun and W. Ecker
15:30 - 16:00 Coffee break
16:00 - 16:40 Paper Session 3
(16:00 - 16:20) Rapid RISC-V Floating Point Vector Simulation, N. Zurstraßen, N. Bosbach, L. Jünger and R. Leupers
(16:20 - 16:40) Flexible front-end for high level synthesis leveraging heterogeneous compilation, G. Lounes, R. Gerzaguet and M. Gautier
16:40 - 16:50 Workshop Closing and Best Paper Award
